1. Field of the invention
The present invention relates generally to a PLL (Phase-Locked Loop) circuit, more particularly, is directed to a PLL circuit which is capable of keeping a phase lock state of PLL even if some failure occurs in an input clock signal.
2. Prior Art
PLL circuits are employed in a variety of data communication devices in order to synchronize an internal clock to a particular clock signal receive from outside. Especially, since a data transmission system requires high reliability, it is necessary for the PLL circuit to maintain the phase lock state even if some failure occurs on incoming lines or the receiving clock signal is extremely deteriorated. For this reason, in most cases, a timing holdover function is provided with the PLL circuit.
FIG. 1 shows one example of a conventional PLL circuit having a timing holdover circuit. Referring to the figure, an output clock signal (b) which a voltage controlled oscillator (VCO) 1 generates is divided through a loop counter 2 to output it to a phase comparator 3. The phase comparator 3 compares the phases of an input clock signal (a) and the output clock signal (b) to output a voltage representing the phase difference to an amplifier 5 through a low pass filter 4. An output voltage of the amplifier 5 is applied to the VCO 1 as a control voltage. The input clock signal (a) is divided by a divider 6 and the output signal of the divider 6 is transferred to the phase comparator 3 through a selector 7.
The timing holdover circuit is formed as follows. A hold timing generator 8 receives a divided clock signal (c) from a divider (or a frequency demultiplier) 6 and outputs a reset timing signal (d) to a hold counter 10 through a switch 9, the reset timing signal (d) indicating phase information of the input clock signal (a). The hold counter 10 is a dividing counter which divides the output clock signal (b) of the VCO 1 by a predetermined number, and is reset by the reset timing signal (d). A dividing ratio of the hold counter 10 is set at the same figure as the loop counter 2. The divided clock signal (f) is output to the selector 7. The selector 7 selects one of the divided clock signal (f) received from the hold counter 10 and the divided clock signal received from the divider 6 according to a fault detection signal (e) and outputs it to the phase comparator 3.
In case of a normal state, the selector 7 selects the divided clock signal received from the divider 6 and the switch 9 is closed to supply the reset timing signal (d) to the hold counter 10. Since the input clock signal (a) is selected, the output clock signal (b) is phase-locked to the input clock signal (a). Moreover, every time receiving the reset timing signal (d) which indicates the phase information of the input clock signal (a), the hold counter 10 updates the clock phase stored therein.
If no input clock signal (a) is received or a large deviation of frequency or phase occurs, the fault detection signal (e) becomes active. When the fault detection signal (e) becomes active, the switch 9 is opened and the selector 7 selects the divided clock signal (f) to output it to the phase comparator 3. The hold counter 10 outputs the divided clock signal (f) corresponding to the reset timing signal (d) which was received just before the fault occurrence. Therefore, the VCO 1 generates the output clock signal (b) on the basis of the divided clock signal (f). In other words, even though any fault occurs on the input clock signal (a), a lock state of PLL can be maintained. However, the conventional PLL circuit mentioned above retains the PLL lock state by using the phase information just before the failure occurs. Therefore, if the input clock signal (a) was deteriorated by the time when the failure occurs, the PLL circuit is locked according to the phase information of a deteriorating input clock.